Electrostatic discharge (ESD) event occurring at the chip level is one of the major causes of integrated circuit failure. To protect integrated circuits from such ESD events, conventional ESD protection circuits that are connected between the input output (I/O) pads and the internal circuits are used to discharge the damaging ESD current to an electrical ground. However, as integrated circuits' size continues to shrink to sub-micron level and the operating speed increases above the gigahertz threshold, higher current densities and lower voltage tolerance are required to reduce noise and power consumption. As a result, it is more difficult to provide ESD protection without affecting the normal operations of these integrated circuits.
Conventional ESD protection circuits often mistake an over-voltage well within the voltage tolerances of the signal bus pads as ESD events, activating a discharge path that draws away current from the internal circuits and thus undermining their performances. For example, the I/O pads of Multi-point Low Voltage Differential Signaling (MLVDS) integrated circuits need to tolerate a voltage from −1.4 V to 3.8 V that is caused by overshoots when the operating power supply levels of the internal circuits are at 0 volts and at 3.3 volts. As the voltage at the I/O pads in MLVDS integrated circuits is lower than 0 Volts in normal operation, diodes in prior art ESD protection circuits can be inadvertently placed in the forward-biased condition and current may flow through these diodes from signal bus pad to electrical ground, thus interfering with normal operation of the internal circuits.
Therefore, there is a need for an ESD protection circuit that can protect integrated circuits from ESD events and that will not discharge at over-voltage events. The present invention meets the above needs.